(1) Field of the Invention
The present invention relates to logic circuits and semiconductor integrated circuits using the same, and more particularly to logic circuits which can be advantageously utilized in multiple input circuits, such as semiconductor memory decoder circuits, provided in an array form, and semiconductor integrated circuits using theame.
(2) Decription of the Related Art
As an example of the prior art multiple input logic circuit, a two-input NAND circuit comprising a bipolar transistor and a MOS transistor (this structure being hereinafter referred to as BiCMOS structure) will now be described. FIG. 1 is circuit diagram showing the NAND circuit. As shown, the NAND circuit comprises a logic circuit stage 1 having a CMOS transistor structure and an output stage 2 having bipolar/MOS transistor 710 structure. Specifically, the logic circuit stage 1 includes a parallel circuit of two p-channel MOS transistors M.sub.23 and M.sub.24 and a series circuit of two n-channel MOS transistors M.sub.21 and M.sub.22, the parallel and series circuits being connected in series in the mentioned order between a high potential power supply line 3 (at a potential V.sub.cc) and a ground line 4. Of the two input signals A and B subjected to logical operation, the signal A is inputted to the gates of the p- and n-channel MOS transistors M.sub.23 and M.sub.21. The input signal B, on the other hand, is inputted to the gates of the p- and n-channel MOS transistors M.sub.24 and M.sub.22. A signal which is produced as a result of the operation, is outputted from the common node of the drains of the two p-channel MOS transistors and the n-channel MOS transistor M.sub.21 and inputted to the output stage 2.
The output stage 2 includes bipolar transistor (hereinafter referred to as BiP transistor) Q.sub.2 and two n-channel MOS transistors M.sub.25 and M.sub.26, these transistors being connected in series in the mentioned order between the power supply line 3 and the ground line 4. The logic signal from the logic circuit stage 1 is inputted to the base of the transistor Q.sub.2. The input signals A and B are also assigned to the gates of the series n-channel MOS transistors M.sub.25 and M.sub.26, respectively. This two-input NAND circuit having the BiCMOS structure provides its output signal X.sub.0 from an output terminal 5, which is constituted by the nodal point between the drain of the n-channel MOS transistor M.sub.25 and the emitter of the BiP transistor Q.sub.2 in the output stage 2.
In the circuit shown in FIG. 1, when the signals A and B both become "high", the series n-channel MOS transistors M.sub.21 and M.sub.22 both become "on", while the parallel p-channel MOS transistors M.sub.23 and M.sub.24 both become "off". The base of the BiP transistor Q.sub.2 is thus brought down to the ground potential so that this transistor is turned off. At this time, the series n-channel MOS transistors M.sub.25 and M.sub.26 also both become "on" to cause the charge to a load (not shown) to be discharged through them, thus pulling down the output signal X.sub.0 to be "low".
When either of the signals A and B becomes "low", either of the n-channel MOS transistors M.sub.21 and M.sub.22 becomes "off", and these transistors thus cannot pull down the base potential on the BiP transistor Q.sub.2. Either of the p-channel MOS transistors M.sub.23 and M.sub.24, on the other hand, is turned on, and these transistors thus pull up the base potential on the BiP transistor Q.sub.2. The BiP transistor Q.sub.2 is thus turned on with its base potential pulled up to V.sub.cc. Since either of the series n-channel MOS transistors M.sub.25 and M.sub.26 is turned off at this time, no charge is pulled through the output terminal 5. As the result of charging by the BiP transistor Q.sub.2, the output signal X.sub.0 becomes "high".
It is to be understood that the output X.sub.0 of the circuit shown in FIG. 1 has the NAND logic such that it becomes "low" when a plurality of inputs all become "high" and becomes "high" otherwise. The above logic circuit is used frequently for decoder circuits assembled in semiconductor memories or the like. The circuit operation in such a case is featured in that only one of a number of NAND gates in an array provides a "low" output as a selected output while the other NAND gate outputs are all "high" as non-selected outputs. The decoder circuit can finally select a memory cell corresponding to an inputted address with a connection of a plurality of stages of such NAND gates.
In the above NAND circuit, the output signal X.sub.0 is pulled up to "high" by the BiP transistor Q.sub.2 whose base current is supplied from at least either one of the p-channel MOS transistors M.sub.23 and M.sub.24. Thus, high current capacity and high operation speed can be obtained. However, the output signal X.sub.0 is pulled down by the pull-down of the base potential on the BiP transistor Q.sub.2 by the series n-channel MOS transistors M.sub.21 and M.sub.22 and also by the pullout of charge from the output load by the series n-channel MOS transistors M.sub.25 and M.sub.26. This is equivalent to doubling of the n-channel MOS transistor gate length and reduction to one half of the current capacity of the n-channel MOS transistor drain current. To compensate for the reduction to one half of the n-channel MOS transistor drain current, usually the gate width of the n-channel MOS transistors M.sub.21, M.sub.22, M.sub.25 and M.sub.26 is made large so as to increase the current capacity to prevent the speed-down of the pull-up as much as possible. However, by increasing the gate width, the input capacitance viewed from the input signal is increased resulting in a delay in the operation of a preceding logic circuit stage (not shown). Where a plurality of logic gate stages are present, it is necessary for the high speed operation of the circuit to improve the fan-out characteristic, i.e., the relation between the ratio of the input capacitance to the output load capacitance and the delay time, but this has been seriously impeded by the capacity reduction of the series n-channel MOS transistors M.sub.21, M.sub.22, M.sub.25 and M.sub.25.
In the decoder circuit, the operation speed of the memory cell selection which is the purpose of the circuit, is greatly dependent on the delay time in the selected signal output. The selection is effected for the pull-down of the output by the series n-channel MOS transistors M.sub.21 and M.sub.22 and also M.sub.25 and M.sub.26 (or for the pull-up of the output by series p-channel MOS transistors in a NOR circuit). Therefore, the operation speed is greatly influenced by the reduction of the current capacity due to the series connection of MOS transistors.